http://bwrc.eecs.berkeley.edu/People/Grad_Students/wrdavis/research/ee241/ee241_report.html
http://bwrc.eecs.berkeley.edu/People/Grad_Students/wrdavis/research/ee241/ee241_report.html
It tells you about PIM, programmable interconnect matrix. Important points from this report are:
1. the analysis of conditions leading to glitch (determining max input voltage to avoid glitch)
2. calculation of coupling capacitance, leading to finding optimum wire width/pitch
3. layout and area considerations during design
Tuesday, March 20, 2007
Monday, December 18, 2006
Interconnects... speed or power?
For general integrated circuit logics, why are low voltage being used?
- First reason: to save power.
- It follows CMOS technology scaling. That is, shrinking sizes of transistor dimensions. Which means, more transistors can be fit into a chip. Which also means, chips can get smarter, and faster at the same time.
But, what about low voltage interconnects? What about on-chip wires??
- Yes, their size won't get smaller. In fact, they will get more complex and probably longer since you will now have much more things to connect to inside a chip, and not to mention the fact that they make chips a bit bigger nowadays?
- So, yes. It's not a good news for interconnects. Yes, low voltage will save power too in the case of interconnects, BUT due to the above circumstances, longer delays will occur... and higher noise interference?
So at least, we had identified two contradictive problems for interconnects: speed and power.
Naturally, if you just follow the technology scaling trend without doing any clever solutions to the interconnect, then these interconnects will get slower and more power consumptive.
Now, it all depends on what is it that you actually want? Do you want speed? Or are you more concerned with power?
- First reason: to save power.
- It follows CMOS technology scaling. That is, shrinking sizes of transistor dimensions. Which means, more transistors can be fit into a chip. Which also means, chips can get smarter, and faster at the same time.
But, what about low voltage interconnects? What about on-chip wires??
- Yes, their size won't get smaller. In fact, they will get more complex and probably longer since you will now have much more things to connect to inside a chip, and not to mention the fact that they make chips a bit bigger nowadays?
- So, yes. It's not a good news for interconnects. Yes, low voltage will save power too in the case of interconnects, BUT due to the above circumstances, longer delays will occur... and higher noise interference?
So at least, we had identified two contradictive problems for interconnects: speed and power.
Naturally, if you just follow the technology scaling trend without doing any clever solutions to the interconnect, then these interconnects will get slower and more power consumptive.
Now, it all depends on what is it that you actually want? Do you want speed? Or are you more concerned with power?
Monday, November 27, 2006
Why i made this blog...
1. I'm dead meat. My thesis is going nowhere.
2. I like blogging, but it's a bit time consuming... most of the time. That's why i haven't been updating as often as i used to on my usual blog.
3. I keep forgeting things.. and when this happens on my research plans, my thesis will stop... for a week or two.
4. So... here you are... a special blog, just to make sure my thesis will progress as planned.
Hmm... so let me make a promise. At least to myself and those who happens to come across this stupid blog... from now on, I, Astria Nur Irfansyah, will update this blog on a daily basis. And the update should better be a report or progress on my thesis, not just stories, like ... "oh i went to the movies on my weekend so i didn't have time to work on my thesis..." or "i broke 5 pallets last night, and packed the entire youghurt and juice aisle, so i was too tired to come to uni".. or other ridicolous excuses.
As a start, i will begin by telling you the topic of my boring thesis:
2. I like blogging, but it's a bit time consuming... most of the time. That's why i haven't been updating as often as i used to on my usual blog.
3. I keep forgeting things.. and when this happens on my research plans, my thesis will stop... for a week or two.
4. So... here you are... a special blog, just to make sure my thesis will progress as planned.
Hmm... so let me make a promise. At least to myself and those who happens to come across this stupid blog... from now on, I, Astria Nur Irfansyah, will update this blog on a daily basis. And the update should better be a report or progress on my thesis, not just stories, like ... "oh i went to the movies on my weekend so i didn't have time to work on my thesis..." or "i broke 5 pallets last night, and packed the entire youghurt and juice aisle, so i was too tired to come to uni".. or other ridicolous excuses.
As a start, i will begin by telling you the topic of my boring thesis:
"Low Swing On-Chip Interconnects"See you tomorrow.
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